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<div class="header">
  <div class="summary">
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle">
<div class="title">EZI2C Activity Status<div class="ingroups"><a class="el" href="group__group__scb.html">SCB          (Serial Communication Block)</a> &raquo; <a class="el" href="group__group__scb__ezi2c.html">EZI2C (SCB)</a> &raquo; <a class="el" href="group__group__scb__ezi2c__macros.html">Macros</a></div></div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p>Macros to check current EZI2C activity slave status returned by <a class="el" href="group__group__scb__ezi2c__slave__functions.html#ga8cd24e8c6c0bb996f6266443e1353f39">Cy_SCB_EZI2C_GetActivity</a> function. </p>
<p>Each EZI2C slave status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga4aca0331d49ac511d15bc797b1f22960"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__ezi2c__macros__get__activity.html#ga4aca0331d49ac511d15bc797b1f22960">CY_SCB_EZI2C_STATUS_READ1</a>&#160;&#160;&#160;(0x01UL)</td></tr>
<tr class="memdesc:ga4aca0331d49ac511d15bc797b1f22960"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Read transfer intended for the primary slave address is complete.  <a href="#ga4aca0331d49ac511d15bc797b1f22960">More...</a><br /></td></tr>
<tr class="separator:ga4aca0331d49ac511d15bc797b1f22960"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3f22409e7776d9d7dea6d88f6424020a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__ezi2c__macros__get__activity.html#ga3f22409e7776d9d7dea6d88f6424020a">CY_SCB_EZI2C_STATUS_WRITE1</a>&#160;&#160;&#160;(0x02UL)</td></tr>
<tr class="memdesc:ga3f22409e7776d9d7dea6d88f6424020a"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Write transfer intended for the primary slave address is complete.  <a href="#ga3f22409e7776d9d7dea6d88f6424020a">More...</a><br /></td></tr>
<tr class="separator:ga3f22409e7776d9d7dea6d88f6424020a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga625c2cc11c16d3ac8baaf2440d6be804"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__ezi2c__macros__get__activity.html#ga625c2cc11c16d3ac8baaf2440d6be804">CY_SCB_EZI2C_STATUS_READ2</a>&#160;&#160;&#160;(0x04UL)</td></tr>
<tr class="memdesc:ga625c2cc11c16d3ac8baaf2440d6be804"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Read transfer intended for the secondary slave address is complete.  <a href="#ga625c2cc11c16d3ac8baaf2440d6be804">More...</a><br /></td></tr>
<tr class="separator:ga625c2cc11c16d3ac8baaf2440d6be804"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6a16c711c82365de7cff305a3675f355"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__ezi2c__macros__get__activity.html#ga6a16c711c82365de7cff305a3675f355">CY_SCB_EZI2C_STATUS_WRITE2</a>&#160;&#160;&#160;(0x08UL)</td></tr>
<tr class="memdesc:ga6a16c711c82365de7cff305a3675f355"><td class="mdescLeft">&#160;</td><td class="mdescRight">The Write transfer intended for the secondary slave address is complete.  <a href="#ga6a16c711c82365de7cff305a3675f355">More...</a><br /></td></tr>
<tr class="separator:ga6a16c711c82365de7cff305a3675f355"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga748ebd94817f62e09cf408412c54915b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__ezi2c__macros__get__activity.html#ga748ebd94817f62e09cf408412c54915b">CY_SCB_EZI2C_STATUS_BUSY</a>&#160;&#160;&#160;(0x10UL)</td></tr>
<tr class="memdesc:ga748ebd94817f62e09cf408412c54915b"><td class="mdescLeft">&#160;</td><td class="mdescRight">A transfer intended for the primary address or secondary address is in progress.  <a href="#ga748ebd94817f62e09cf408412c54915b">More...</a><br /></td></tr>
<tr class="separator:ga748ebd94817f62e09cf408412c54915b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b63d8bea0972f185377db79852e44b1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__scb__ezi2c__macros__get__activity.html#ga5b63d8bea0972f185377db79852e44b1">CY_SCB_EZI2C_STATUS_ERR</a>&#160;&#160;&#160;(0x20UL)</td></tr>
<tr class="memdesc:ga5b63d8bea0972f185377db79852e44b1"><td class="mdescLeft">&#160;</td><td class="mdescRight">An error occurred during a transfer intended for the primary or secondary slave address.  <a href="#ga5b63d8bea0972f185377db79852e44b1">More...</a><br /></td></tr>
<tr class="separator:ga5b63d8bea0972f185377db79852e44b1"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga4aca0331d49ac511d15bc797b1f22960"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga4aca0331d49ac511d15bc797b1f22960">&#9670;&nbsp;</a></span>CY_SCB_EZI2C_STATUS_READ1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_EZI2C_STATUS_READ1&#160;&#160;&#160;(0x01UL)</td>
        </tr>
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</div><div class="memdoc">

<p>The Read transfer intended for the primary slave address is complete. </p>
<p>The error condition status bit must be checked to ensure that the Read transfer was completed successfully. </p>

</div>
</div>
<a id="ga3f22409e7776d9d7dea6d88f6424020a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga3f22409e7776d9d7dea6d88f6424020a">&#9670;&nbsp;</a></span>CY_SCB_EZI2C_STATUS_WRITE1</h2>

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<div class="memproto">
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          <td class="memname">#define CY_SCB_EZI2C_STATUS_WRITE1&#160;&#160;&#160;(0x02UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The Write transfer intended for the primary slave address is complete. </p>
<p>The buffer content was modified. The error condition status bit must be checked to ensure that the Write transfer was completed successfully. </p>

</div>
</div>
<a id="ga625c2cc11c16d3ac8baaf2440d6be804"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga625c2cc11c16d3ac8baaf2440d6be804">&#9670;&nbsp;</a></span>CY_SCB_EZI2C_STATUS_READ2</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define CY_SCB_EZI2C_STATUS_READ2&#160;&#160;&#160;(0x04UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The Read transfer intended for the secondary slave address is complete. </p>
<p>The error condition status bit must be checked to ensure that the Read transfer was completed successfully. </p>

</div>
</div>
<a id="ga6a16c711c82365de7cff305a3675f355"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6a16c711c82365de7cff305a3675f355">&#9670;&nbsp;</a></span>CY_SCB_EZI2C_STATUS_WRITE2</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_EZI2C_STATUS_WRITE2&#160;&#160;&#160;(0x08UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>The Write transfer intended for the secondary slave address is complete. </p>
<p>The buffer content was modified. The error condition status bit must be checked to ensure that the Write transfer was completed successfully. </p>

</div>
</div>
<a id="ga748ebd94817f62e09cf408412c54915b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga748ebd94817f62e09cf408412c54915b">&#9670;&nbsp;</a></span>CY_SCB_EZI2C_STATUS_BUSY</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_EZI2C_STATUS_BUSY&#160;&#160;&#160;(0x10UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>A transfer intended for the primary address or secondary address is in progress. </p>
<p>The status bit is set after an address match and cleared on a Stop or ReStart condition. </p>

</div>
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<a id="ga5b63d8bea0972f185377db79852e44b1"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga5b63d8bea0972f185377db79852e44b1">&#9670;&nbsp;</a></span>CY_SCB_EZI2C_STATUS_ERR</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define CY_SCB_EZI2C_STATUS_ERR&#160;&#160;&#160;(0x20UL)</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>An error occurred during a transfer intended for the primary or secondary slave address. </p>
<p>The sources of the error are: a misplaced Start or Stop condition or lost arbitration while the slave drives SDA. When CY_SCB_EZI2C_STATUS_ERR is set, the slave buffer may contain an invalid byte. Discard the buffer content in this case. </p>

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